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October 2006
HYS[64/72]T256020EU-[25F/2.5]-B HYS[64/72]T256020EU-[3/3S]-B HYS[64/72]T256020EU-3.7-B
240-Pin unbuffered DDR2 SDRAM Modules DDR2 SDRAM UDIMM SDRAM RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
HYS[64/72]T256020EU-[25F/2.5]-B, HYS[64/72]T256020EU-[3/3S]-B, HYS[64/72]T256020EU-3.7-B Revision History: 2006-10, Rev. 1.0 Page All 17-18 36-38 All 23 All 43, 44 Subjects (major changes since last revision) Adapted internet edition Updated Clock Load Tables and Notes of Block Diagrams
IDD currents update
Qimonda update Modified AC Timing Parameters Updated for speed -5 Added IDD Current Values for speed -3S and -3.7
Previous Revision: 2006-09, Rev. 0.61
Previous Revision: 2006-08, Rev. 0.6
Previous Revision: Rev. 0.5
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 10262006-SX8C-DEY8
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main characteristics.
1.1
Features
* * * * * * * * * * Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM UDIMM and EDIMM Dimensions (nominal): 30 mm high, 133.35 mm wide Based on standard reference layouts Raw Card "E" and "G" RoHS compliant products1)
* 240-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2 SDRAM memory modules. * 256M x 64 and 256M x72 module organization,and 128M x 8 chip organization * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * 2 GB Built with 1Gbit DDR2 SDRAMs in and P-TFBGA-68-6 chipsize packages * All speed grades faster than DDR400 comply with DDR400 timing specifications. * Programmable CAS Latencies (3, 4, 5 and 6), Burst Length (8 & 4) and Burst Type * Average Refresh Period 7.8 s at a TCASE lower than 85C, 3.9s between 85C and 95C.
TABLE 1
Performance Table
Product Type Speed Code Speed Grade Max. Clock Frequency @CL6 @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -25F PC2-6400 5-5-5 -2.5 PC2-6400 6-6-6 400 333 266 200 15 15 45 60 -3 PC2-5300 4-4-4 - 333 333 200 12 12 45 57 -3S PC2-5300 5-5-5 - 333 266 200 15 15 45 60 -3.7 PC2-4200 4-4-4 - 266 266 200 15 15 45 60 Unit -- MHz MHz MHz MHz ns ns ns ns
fCK6 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
400 400 266 200 12.5 12.5 45 57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
1.2
Description
are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer.
The QIMONDA HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B module family are unbuffered DIMM modules "UDIMMs" with 30 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 256M x 64 (2 GB) and as ECC modules in 256M x 72 (2 GB) organization and density, intended for mounting into 240-pin connector sockets. The memory array is designed with 1-Gbit Double-Data-RateTwo (DDR2) Synchronous DRAMs. Decoupling capacitors
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1) PC2-6400 HYS64T256020EU-25F-B HYS72T256020EU-25F-B PC2-6400 HYS64T256020EU-2.5-B HYS72T256020EU-2.5-B PC2-5300 HYS64T256020EU-3-B HYS72T256020EU-3-B PC2-5300 HYS64T256020EU-3S-B HYS72T256020EU-3S-B PC2-4200 HYS64T256020EU-3.7-B HYS72T256020EU-3.7-B 2 GB 2Rx8 PC2-4200U-444-12-E0 2 GB 2Rx8 PC2-4200E-444-12-G0 2 Ranks, Non-ECC 2 Ranks, ECC 1 Gbit (x8) 1 Gbit (x8) 2 GB 2Rx8 PC2-5300U-555-12-E0 2 GB 2Rx8 PC2-5300E-555-12-G0 2 Ranks, Non-ECC 2 Ranks, ECC 1 Gbit (x8) 1 Gbit (x8) 2 GB 2Rx8 PC2-5300U-444-12-E0 2 GB 2Rx8 PC2-5300E-444-12-G0 2 Ranks, Non-ECC 2 Ranks, ECC 1 Gbit (x8) 1 Gbit (x8) 2 GB 2Rx8 PC2-6400U-666-12-E0 2 GB 2Rx8 PC2-6400E-666-12-G0 2 Ranks, Non-ECC 2 Ranks, ECC 1 Gbit (x8) 1 Gbit (x8) 2 GB 2Rx8 PC2-6400U-555-12-E0 2 GB 2Rx8 PC2-6400E-555-12-G0 2 Ranks, Non-ECC 2 Ranks, ECC 1 Gbit (x8) 1 Gbit (x8) Compliance Code2) Description SDRAM Technology
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T256020EU-3.7-B, indicating Rev. "B" dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200U-444-12-E0", where 4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and "444-12" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "B".
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
TABLE 3
Address Format
DIMM Density 2 GByte 2 GByte Module Organization 128M x 64 128M x 72 Memory Ranks 2 2 ECC/ Non-ECC Non-ECC ECC # of SDRAMs # of row/bank/column bits 16 18 14/3/10 14/3/10 Raw Card E G
TABLE 4
Components on Modules
Product Type1) HYS64T256020EU HYS72T256020EU DRAM Components1) HYB18T1G800BF HYB18T1G800BF DRAM Density 1 Gbit 1 Gbit DRAM Organisation 128M x 8 128M x 8 Note2)
1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
2
2.1
Pin Configuration
Pin Configuration
This chapter contains the pin configuration.
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1 for non-ECC modules (x64) and Figure 2 for ECC modules (x72).
TABLE 5
Pin Configuration of UDIMM
Ball No. Clock Signals 185 137 220 186 138 221 52 171 CK0 CK1 CK2 CK0 CK1 CK2 CKE0 CKE1 NC Control Signals 193 76 S0# S1# NC 192 74 73 Address Signals 71 190 54 BA0 BA1 BA2 NC I I I NC SSTL SSTL SSTL -- Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS Not Connected Less than 1Gb DDR2 SDRAMS Bank Address Bus 1:0 RAS CAS WE I I NC I I I SSTL SSTL -- SSTL SSTL SSTL Chip Select Rank 1:0 Note: 2 Ranks module Not Connected Note: 1 Rank module Row Address Strobe Column Address Strobe Write Enable I I I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- Clock Enable Rank 1:0 Note: 2 Ranks module Not Connected Note: 1 Rank module Clock Signals 2:0, Complement Clock Signals 2:0 Name Pin Type Buffer Type Function
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Ball No. 188 183 63 182 61 60 180 58 179 177 70 57 176 196
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC
Pin Type I I I I I I I I I I I I I I I NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL --
Function Address Bus 12:0
Address Signal 13 Note: 1 Gbit based module and 512M x4/x8 Not Connected Note: Module based on 1 Gbit x16 Module based on 512 Mbit x16 or smaller Address Signal 14 Note: Modules based on 2 Gbit Not Connected Note: Modules based on 1 Gbit or smaller Data Bus 63:0 Data Input/Output pins
174
A14 NC
I NC
SSTL --
Data Signals 3 4 9 10 122 123 128 129 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
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Ball No. 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 206 89 90 95 96 208 209 214 215
Name DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0 Data Input/Output pins
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Ball No. 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Check Bit Signals 42
Name DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 NC
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL --
Function Data Bus 63:0 Data Input/Output pins
Check Bit 0 Note: ECC type module only Not Connected Note: ECC type module only Check Bit 1 Note: ECC type module only Not Connected Note: ECC type module only Check Bit 2 Note: ECC type module only Not Connected Note: ECC type module only Check Bit 3 Note: ECC type module only Not Connected Note: ECC type module only Check Bit 4 Note: ECC type module only Not Connected Note: ECC type module only Check Bit 5 Note: ECC type module only Not Connected Note: ECC type module only
43
CB1 NC
48
CB2 NC
49
CB3 NC
161
CB4 NC
162
CB5 NC
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Ball No. 167
Name CB6 NC
Pin Type I/O NC I/O NC
Buffer Type SSTL -- SSTL --
Function Check Bit 6 Note: ECC type module only Not Connected Note: ECC type module only Check Bit 7 Note: ECC type module only Not Connected Note: Non-ECC module Data Strobe Bus 8:0
168
CB7 NC
Data Strobe Bus 7 16 28 37 84 93 105 114 46 6 15 27 36 83 92 104 113 45 Data Mask Signals 125 134 146 155 202 211 223 232 164 EEPROM 120 119 SCL SDA I I/O CMOS OD Serial Bus Clock Serial Bus Data DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask Bus 8:0 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Complement Data Strobe Bus 8:0
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Ball No. 239 240 101 Power Supplies 1 238 51,56,62,72,75,, 78,170,175,181,, 191,194 53,59,64,67,69,, 172,178,184,187, 189,197 2,5,8,11,14,17,, 20,23,26,29,32, 35,38,41,44,47,, 50,65,66,79,82, 85,88,91,94,97,, 100,103,106, 109,112,115,118, 121,124,127,, 130,133,136,139, 142,145,148,, 151,154,157,160, 163,166,169, 198,201,204,207, 210,213,216,, 219,222,225,228, 231,234,237 Other Pins 195 77
Name SA0 SA1 SA2
Pin Type I I I
Buffer Type CMOS CMOS CMOS -- -- --
Function Serial Address Select Bus 2:0
VREF AI VDDSPD PWR VDDQ PWR
I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply
VDD
PWR
--
Power Supply
VSS
GND
--
Ground Plane
ODT0 ODT1 NC
I I NC NC
SSTL SSTL -- --
On-Die Termination Control 0 On-Die Termination Control 1 Note: 2 Rank modules Not Connected Note: 1 Rank modules Not connected
18,19,55,68,102,1 NC 26,135,147, 156,165,173,203, 212, 224,233
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TABLE 6
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and allows multiple devices to share as a wire-OR.
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Pin Configuration UDIMM x64 (240 Pin)
FIGURE 1
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Pin Configuration UDIMM x72 (240 Pin)
FIGURE 2
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3
3.1
Electrical Characteristics
Absolute Maximum Ratings
TABLE 8
Absolute Maximum Ratings
This chapter lists the electrical characteristics.
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature -55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
VDD VDDQ VDDL VIN, VOUT TSTG
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS
-1.0 -0.5 -0.5 -0.5
V V V V C
1) 1)2) 1)2) 1) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max. 95 C
1)2)3)4)
Unit
Note
TOPER
Operating Temperature
0
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
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3.2
DC Operating Conditions
TABLE 10
Operating Conditions
This chapter contains the DC operating conditions tables.
Parameter
Symbol
Values Min. Max. +65 +95 +100 +105 90
Unit
Note
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
1) 2) 3) 4)
TOPR TCASE TSTG
PBar
0 0 - 50 +69 10
C C C kPa %
5) 1)2)3)4)
HOPR
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature Range all DRAM specifications will be supported Above 85 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%. 5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Typ. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V
3) 1) 2)
Unit
Note
In / Output Leakage Current -5 -- 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30
VDDQ + 0.3 VREF - 0.125
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3.3
Timing Characteristics
This chapter describes the timing characteristics.
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with tRAS = 40ns). Speed Grade Definition: Table 12 for DDR2-800, Table 13 for DDR2-667 and Table 14 DDR2-533C.
TABLE 12
Speed Grade Definition Speed Bins for DDR2-800
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-800D -2.5F 5-5-5 Min. 5 3.75 2.5 2.5 45 57.5 12.5 12.5 Max. 8 8 8 8 70000 -- -- -- DDR2-800E -2.5 6-6-6 Min. 5 3.75 3 2.5 45 60 15 15 Max. 8 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 13
Speed Grade Definition Speed Bins for DDR2-667
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Symbol DDR2-667C -3 4-4-4 Min. 5 3 3 Max. 8 8 8 DDR2-667D -3S 5-5-5 Min. 5 3.75 3 Max. 8 8 8 Unit Note
tCK
-- ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK
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Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-667C -3 4-4-4 Min. 45 57 12 12 Max. 70000 -- -- -- DDR2-667D -3S 5-5-5 Min. 45 60 15 15 Max. 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns
1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) . 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 14
Speed Grade Definition Speed Bins for DDR2-533C
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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3.3.2
Component AC Timing Parameters
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2-800
Timing Parameters: Table 15 for DDR2-800, Table 16 for DDR2-667 and Table 17 for DDR2-533C.
Parameter
Symbol
DDR2-800 Min. Max. +400 +350 0.52 0.52 8000 -- -- -- --
Unit
Note1)2)3)4)5)6)7)
8)
DQ output access time from CK / CK DQS output access time from CK / CK Average clock high pulse width Average clock low pulse width
tAC tDQSCK tCH.AVG
-400 -350 0.48 0.48 2500 50 125 0.6 0.35 --
ps ps
9) 9)
tCK.AVG tCK.AVG
ps ps ps
10)11)
10)11) 10)11) 12)13)14) 13)14)15)
tCL.AVG Average clock period tCK.AVG DQ and DM input setup time tDS.BASE DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK / CK tHZ DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP
DQ hold skew factor DQ/DQS output hold time from DQS Write command to DQS associated clock edges
tCK.AVG tCK.AVG
ps ps ps ps ps ps ps nCK
9)16) 9)16) 9)16) 17) 18)
tAC.MIN 2 x tAC.MIN
-- Min(tCH.ABS, tCL.ABS) --
tAC.MAX tAC.MAX
tAC.MAX 200 __ 300 -- + 0.25 -- -- -- -- 0.6 -- -- -- 1.1 0.6 -- -- --
tQHS tQH
WL
19) 20)
tHP - tQHS
RL - 1 - 0.25 0.35 0.35 0.2 0.2 0.4 0.35 175 250 0.9 0.4 7.5 10 35
DQS latching rising transition to associated clock tDQSS edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products
tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG
ps ps
21)
tDQSH tDQSL tDSS tDSH tWPST tWPRE tIS.BASE tIH.BASE tRPRE tRPST tRRD tRRD
21) 21)
22)23) 23)24) 25)26) 25)27) 28)
tCK.AVG tCK.AVG
ns ns ns
28)
Four Activate Window for 1KB page size products tFAW
28)
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Parameter
Symbol
DDR2-800 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- 12 12 --
Unit
Note1)2)3)4)5)6)7)
8)
Four Activate Window for 2KB page size products tFAW
45 2 15 WR + tnRP 7.5 7.5
ns nCK ns nCK ns ns ns nCK nCK nCK nCK nCK nCK ns ns ns
28)
tCCD tWR Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay tWTR Internal Read to Precharge command delay tRTP Exit self-refresh to a non-read command tXSNR Exit self-refresh to read command tXSRD Exit precharge power-down to any valid tXP
CAS to CAS command delay Write recovery time command (other than NOP or Deselect) Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) CKE minimum pulse width ( high and low pulse width) Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW
28) 29)30) 28)31) 28) 28)
tRFC +10
200 2 2 8 - AL 3 2 0 0
tXARD tXARDS tCKE tMRD tMOD tOIT tDELAY
32)
28) 28)
tIS + tCK .AVG + tIH
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 4. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
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14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 4. 16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 5. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 5. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.
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TABLE 16
DRAM Component Timing Parameter by Speed Grade - DDR2-667
Parameter Symbol DDR2-667 Min. DQ output access time from CK / CK DQS output access time from CK / CK Average clock high pulse width Average clock low pulse width Max. +450 +400 0.52 0.52 8000 -- -- -- -- ps ps
9) 9)
Unit
Note1)2)3)4)5)6)7)
8)
tAC tDQSCK tCH.AVG
-450 -400 0.48 0.48 3000 100 175 0.6 0.35 --
tCK.AVG tCK.AVG
ps ps ps
10)11)
10)11)
tCL.AVG Average clock period tCK.AVG DQ and DM input setup time tDS.BASE DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK / CK tHZ DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP
DQ hold skew factor DQ/DQS output hold time from DQS Write command to DQS associated clock edges
12)13)14) 13)14)15)
tCK.AVG tCK.AVG
ps ps ps ps ps ps ps nCK
9)16) 9)16) 9)16) 17) 18)
tAC.MIN 2 x tAC.MIN
-- Min(tCH.ABS, tCL.ABS) --
tAC.MAX tAC.MAX tAC.MAX
240 __ 340 -- + 0.25 -- -- -- -- 0.6 -- -- -- 1.1 0.6 -- -- -- -- -- --
tQHS tQH
WL
19) 20)
tHP - tQHS
RL-1 - 0.25 0.35 0.35 0.2 0.2 0.4 0.35 200 275 0.9 0.4 7.5 10 37.5 50 2 15
DQS latching rising transition to associated clock tDQSS edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products
tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG
ps ps
21)
tDQSH tDQSL tDSS tDSH tWPST tWPRE tIS.BASE tIH.BASE tRPRE tRPST tRRD tRRD
21) 21)
22)23) 23)24) 25)26) 25)27) 28)
tCK.AVG tCK.AVG
ns ns ns ns nCK ns
28)
Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW CAS to CAS command delay Write recovery time
28) 28)
tCCD tWR
28)
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Parameter
Symbol
DDR2-667 Min. Max. -- -- -- -- -- -- -- -- -- -- 12 12 --
Unit
Note1)2)3)4)5)6)7)
8)
Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay Internal Read to Precharge command delay Exit self-refresh to a non-read command Exit self-refresh to read command Exit precharge power-down to any valid command (other than NOP or Deselect) Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) CKE minimum pulse width ( high and low pulse width) Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW
WR + tnRP 7.5 7.5
nCK ns ns ns nCK nCK nCK nCK nCK nCK ns ns ns
29)30) 28)31) 28) 28)
tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS tCKE tMRD tMOD tOIT tDELAY
tRFC +10
200 2 2 7 - AL 3 2 0 0
32)
28) 28)
tIS + tCK .AVG + tIH
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 4. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing.
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15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 4. 16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 5. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 5. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.
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FIGURE 3
Method for calculating transitions and endpoint
FIGURE 4
Differential input waveform timing - tDS and tDS
FIGURE 5
Differential input waveform timing - tlS and tlH
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TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2-533
Parameter Symbol DDR2-533 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- -- -- ps Unit Note1)2)3)4)5)
6)7)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-500 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
8)18)
tIS + tCK + tIH
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 37.5 50 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN
9)
10)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
11)
tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS(base)
tCK
ps
tCK
ps
11)
tCK
ps ps
11)
DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS
11)
tDSH
tCK tCK
ns ns -- ps ps
13) 12) 13) 11)
DQS falling edge to CK setup time (write cycle) tDSS
tFAW tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH
tAC.MAX
-- -- --
tCK
ps ps ps
11) 14) 14)
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 --
tCK
ns --
tHP -tQHS
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Parameter
Symbol
DDR2-533 Min. Max. 400 7.8 3.9 -- -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- --
Unit
Note1)2)3)4)5)
6)7)
Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
tQHS tREFI tRFC tRP tRP tRPRE tRPST tRRD tRTP tWPRE tWPST tWR
WR
-- -- -- 127.5
ps s s ns ns ns
14)15) 16)18) 17)
tRP + 1tCK
15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15
tCK tCK
ns ns ns
14) 14) 14)18) 16)20)
tCK tCK
ns
19)
tWR/tCK
7.5 2 6 - AL 2
tCK
ns
20)
tWTR tXARD tXARDS tXP tXSNR tXSRD
21) 22)
tCK tCK tCK
ns
22)
tRFC +10
200
tCK
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
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13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 15) 0 C TCASE 85 C 16) 85 C < TCASE 95 C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 "Ordering Information for RoHS Compliant Products" on Page 4. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied.
3.3.3
ODT AC Electrical Characteristics
TABLE 18
ODT AC Character. and Operating Conditions for DDR2-667 & DDR2-800
ODT AC Character. & Operating Conditions: Table 18 for DDR2-667 & DDR2-800 and Table 19 for DDR2-533 & DDR2-400
Symbol
Parameter / Condition
Values Min. Max. 2
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
nCK ns ns nCK ns ns nCK nCK
1) 1)2) 1) 1) 1)3) 1) 1) 1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns
2.5
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG+ tEPR.2PER(MIN). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG = 3 ns is assumed, tAOFD= 1.5 ns (0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edge.
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TABLE 19
ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400
Symbol Parameter / Condition Values Min. Max. 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns
2.5
tCK
ns ns
2)
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
tCK tCK
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
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3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions. * Table 20 "IDD Measurement Conditions" on Page 30 * Table 22 "IDD Specification for HYS[64/72]T256020EU-[25F/2.5]-B" on Page 32 * Table 23 "IDD Specification for HYS[64/72]T256020EU-[3/3S]-B" on Page 33 * Table 24 "IDD Specification for HYS[64/72]T256020EU-3.7-B" on Page 34
TABLE 20
IDD Measurement Conditions
Parameter Symbol Note
1)2)3)4)5)
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD2P IDD2Q
IDD3N
Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current - Burst Read IDD4R All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX; tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
6)
IDD4W
IDD5B
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Parameter Distributed Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Symbol Note
1)2)3)4)5)
IDD5D
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max. All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 21 4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6)
5) For details and notes see the relevant Qimonda component data sheet 6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 21
Definitions for IDD
Parameter LOW STABLE FLOATING SWITCHING Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
Inputs are stable at a HIGH or LOW level Inputs are VREF = VDDQ /2 Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes
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TABLE 22
IDD Specification for HYS[64/72]T256020EU-[25F/2.5]-B
HYS64T256020EU-25F-B HYS64T256020EU-2.5-B HYS72T256020EU-2.5-B Product Type HYS72T256020EU-25F-B Units Note1)
Organization
2 GB x64 2 Ranks -25F
2 GB x72 2 Ranks -25F 1233 1323 1260 216 1170 1620 864 270 1908 1908 2133 234 180 2538
2 GB x64 2 Ranks -2.5 1096 1176 1120 192 1040 1440 768 240 1696 1696 1896 208 160
2 GB x72 2 Ranks -2.5 1230 1320 1260 220 1170 1620 860 270 1910 1910 2130 230 180 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3)4) 3)5) 2) 2) 2) 3)6) 3)6) 2)
2256 2540 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0C TCase 85C
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1096 1176 1120 192 1040 1440 768 240 1696 1696 1896 208 160 2256
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TABLE 23
IDD Specification for HYS[64/72]T256020EU-[3/3S]-B
HYS64T256020EU-3S-B HYS72T256020EU-3S-B HYS64T256020EU-3-B HYS72T256020EU-3-B Product Type Units Note1)
Organization
2 GB x64 2 Ranks -3
2 GB x72 2 Ranks -3 1098 1188 1170 216 1080 1260 810 270 1638 1638 1998 234 180 2178
2 GB x64 2 Ranks -3 976 1056 1040 192 960 1120 720 240 1456 1456 1776 208 160
2 GB x72 2 Ranks -3 1100 1190 1170 220 1080 1260 810 270 1640 1640 2000 230 180 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3)4) 3)5) 2) 2) 2) 3)6) 3)6) 2)
1936 2180 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0C TCase 85C
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
976 1056 1040 192 960 1120 720 240 1456 1456 1776 208 160 1936
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TABLE 24
IDD Specification for HYS[64/72]T256020EU-3.7-B
Product Type Organization HYS64T256020EU-3.7-B 2 GB x64 2 Ranks -3.7 HYS72T256020EU-3.7-B 2 GB x72 2 Ranks -3.7 1008 1053 990 216 900 1080 684 270 1458 1458 1908 234 180 2133 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3)4) 3)5) 2) 2) 2) 3)6) 3)6) 2)
Units
Note1)
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) 2) 3) 4) 5) 6)
896 936 880 192 800 960 608 240 1296 1296 1696 208 160 1896
Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. The other rank is in IDD2P Precharge Power-Down Current mode Both ranks are in the same IDDcurrent mode Fast: MRS(12)=0 Slow: MRS(12)=1 IDD5D and IDD6 values are for 0C TCase 85C
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4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * * * * * Table 25 "SPD codes for HYS[64/72]T256020EU-25F-B" on Page 35 Table 26 "SPD codes for HYS[64/72]T256020EU-2.5-B" on Page 39 Table 27 "SPD codes for HYS[64/72]T256020EU-3-B" on Page 43 Table 28 "SPD codes for HYS[64/72]T256020EU-3S-B" on Page 47 Table 29 "SPD codes for HYS[64/72]T256020EU-3.7-B" on Page 51
TABLE 25
SPD codes for HYS[64/72]T256020EU-25F-B
Product Type Organization HYS64T256020EU-25F-B 2 GByte x64 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-6400U-555 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 25 40 00 82 08 00 00 0C 08 HYS72T256020EU-25F-B 2 GByte x72 2 Ranks (x8) PC2-6400E-555 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 25 40 02 82 08 08 00 0C 08
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
35
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-25F-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-25F-B 2 GByte x72 2 Ranks (x8) PC2-6400E-555 Rev. 1.2 HEX 70 00 02 00 07 25 40 3D 50 32 1E 32 2D 01 17 25 05 12 3C 1E 1E 00 36 39 7F 80 14 1E 00 57 60 5F 40
Label Code JEDEC SPD Revision Byte# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
PC2-6400U-555 Rev. 1.2 HEX 70 00 02 00 07 25 40 3D 50 32 1E 32 2D 01 17 25 05 12 3C 1E 1E 00 36 39 7F 80 14 1E 00 57 60 5F 40
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM)
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
36
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-25F-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-25F-B 2 GByte x72 2 Ranks (x8) PC2-6400E-555 Rev. 1.2 HEX 2B 2E 49 21 4E 25 39 00 00 00 00 12 C0 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 32 35 36 30 32 30 45 55
Label Code JEDEC SPD Revision Byte# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Description T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11
PC2-6400U-555 Rev. 1.2 HEX 2B 2E 49 21 4E 25 39 00 00 00 00 12 AE 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45 55
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
37
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-25F-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-25F-B 2 GByte x72 2 Ranks (x8) PC2-6400E-555 Rev. 1.2 HEX 32 35 46 42 20 20 20 0x xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 84 85 86 87 88 89 90 91 92 93 94 95 - 98 128 255 Description Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank for customer use
PC2-6400U-555 Rev. 1.2 HEX 32 35 46 42 20 20 20 0x xx xx xx xx 00 FF
99 - 127 Not used
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
38
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
TABLE 26
SPD codes for HYS[64/72]T256020EU-2.5-B
Product Type Organization HYS64T256020EU-2.5-B 2 GByte x64 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-6400U-666 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 25 40 00 82 08 00 00 0C 08 70 01 02 00 07 30 45 3D 50 3C 1E 3C HYS72T256020EU-2.5-B 2 GByte x72 2 Ranks (x8) PC2-6400E-666 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 25 40 02 82 08 08 00 0C 08 70 01 02 00 07 30 45 3D 50 3C 1E 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
39
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-2.5-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-2.5-B 2 GByte x72 2 Ranks (x8) PC2-6400E-666 Rev. 1.2 HEX 2D 01 17 25 05 12 3C 1E 1E 00 06 3C 7F 80 14 1E 00 57 60 57 40 2B 2E 49 21 4E 25 36 00 00 00 00 12
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-6400U-666 Rev. 1.2 HEX 2D 01 17 25 05 12 3C 1E 1E 00 06 3C 7F 80 14 1E 00 57 60 57 40 2B 2E 49 21 4E 25 36 00 00 00 00 12
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
40
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-2.5-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-2.5-B 2 GByte x72 2 Ranks (x8) PC2-6400E-666 Rev. 1.2 HEX AD 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 32 35 36 30 32 30 45 55 32 2E 35 42 20 20 20 3x xx xx xx xx
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-6400U-666 Rev. 1.2 HEX 9B 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45 55 32 2E 35 42 20 20 20 3x xx xx xx xx
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
41
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-2.5-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-2.5-B 2 GByte x72 2 Ranks (x8) PC2-6400E-666 Rev. 1.2 HEX 00 FF
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-6400U-666 Rev. 1.2 HEX 00 FF
99 - 127 Not used
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
42
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
TABLE 27
SPD codes for HYS[64/72]T256020EU-3-B
Product Type Organization HYS64T256020EU-3-B 2 GByte x64 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-5300U-444 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 30 45 00 82 08 00 00 0C 08 38 01 02 00 07 30 45 50 60 30 1E 30 HYS72T256020EU-3-B 2 GByte x72 2 Ranks (x8) PC2-5300E-444 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 30 45 02 82 08 08 00 0C 08 38 01 02 00 07 30 45 50 60 30 1E 30
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
43
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3-B 2 GByte x72 2 Ranks (x8) PC2-5300E-444 Rev. 1.2 HEX 2D 01 20 27 10 17 3C 1E 1E 00 06 39 7F 80 18 22 00 56 60 47 37 2B 28 3E 21 42 24 2F 00 00 00 00 12
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-5300U-444 Rev. 1.2 HEX 2D 01 20 27 10 17 3C 1E 1E 00 06 39 7F 80 18 22 00 56 60 47 37 2B 28 3E 21 42 24 2F 00 00 00 00 12
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
44
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3-B 2 GByte x72 2 Ranks (x8) PC2-5300E-444 Rev. 1.2 HEX 71 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 32 35 36 30 32 30 45 55 33 42 20 20 20 20 20 3x xx xx xx xx
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-5300U-444 Rev. 1.2 HEX 5F 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45 55 33 42 20 20 20 20 20 3x xx xx xx xx
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
45
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3-B 2 GByte x72 2 Ranks (x8) PC2-5300E-444 Rev. 1.2 HEX 00 FF
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-5300U-444 Rev. 1.2 HEX 00 FF
99 - 127 Not used
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
46
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
TABLE 28
SPD codes for HYS[64/72]T256020EU-3S-B
Product Type Organization HYS64T256020EU-3S-B 2 GByte x64 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-5300U-555 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 30 45 00 82 08 00 00 0C 08 38 01 02 00 07 3D 50 50 60 3C 1E 3C HYS72T256020EU-3S-B 2 GByte x72 2 Ranks (x8) PC2-5300E-555 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 30 45 02 82 08 08 00 0C 08 38 01 02 00 07 3D 50 50 60 3C 1E 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
47
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3S-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3S-B 2 GByte x72 2 Ranks (x8) PC2-5300E-555 Rev. 1.2 HEX 2D 01 20 27 10 17 3C 1E 1E 00 06 3C 7F 80 18 22 00 56 60 3F 37 2B 28 3E 21 42 24 2C 00 00 00 00 12
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-5300U-555 Rev. 1.2 HEX 2D 01 20 27 10 17 3C 1E 1E 00 06 3C 7F 80 18 22 00 56 60 3F 37 2B 28 3E 21 42 24 2C 00 00 00 00 12
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
48
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3S-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3S-B 2 GByte x72 2 Ranks (x8) PC2-5300E-555 Rev. 1.2 HEX 99 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 32 35 36 30 32 30 45 55 33 53 42 20 20 20 20 3x xx xx xx xx
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-5300U-555 Rev. 1.2 HEX 87 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45 55 33 53 42 20 20 20 20 3x xx xx xx xx
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
49
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3S-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3S-B 2 GByte x72 2 Ranks (x8) PC2-5300E-555 Rev. 1.2 HEX 00 FF
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-5300U-555 Rev. 1.2 HEX 00 FF
99 - 127 Not used
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
50
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
TABLE 29
SPD codes for HYS[64/72]T256020EU-3.7-B
Product Type Organization HYS64T256020EU-3.7-B 2 GByte x64 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-4200U-444 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 3D 50 00 82 08 00 00 0C 08 38 01 02 00 07 3D 50 50 60 3C 1E 3C HYS72T256020EU-3.7-B 2 GByte x72 2 Ranks (x8) PC2-4200E-444 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 3D 50 02 82 08 08 00 0C 08 38 01 02 00 07 3D 50 50 60 3C 1E 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
Rev. 1.0, 2006-10 10262006-SX8C-DEY8
51
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3.7-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3.7-B 2 GByte x72 2 Ranks (x8) PC2-4200E-444 Rev. 1.2 HEX 2D 01 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 00 52 60 37 2A 2B 20 35 21 36 22 25 00 00 00 00 12
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-4200U-444 Rev. 1.2 HEX 2D 01 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 00 52 60 37 2A 2B 20 35 21 36 22 25 00 00 00 00 12
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3.7-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3.7-B 2 GByte x72 2 Ranks (x8) PC2-4200E-444 Rev. 1.2 HEX 9E 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54 32 35 36 30 32 30 45 55 33 2E 37 42 20 20 20 3x xx xx xx xx
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-4200U-444 Rev. 1.2 HEX 8C 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45 55 33 2E 37 42 20 20 20 3x xx xx xx xx
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Product Type Organization
HYS64T256020EU-3.7-B 2 GByte x64 2 Ranks (x8)
HYS72T256020EU-3.7-B 2 GByte x72 2 Ranks (x8) PC2-4200E-444 Rev. 1.2 HEX 00 FF
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-4200U-444 Rev. 1.2 HEX 00 FF
99 - 127 Not used
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
5
Package Outlines
FIGURE 6
Package Outline Raw Card E LG-DIM-240-9
This chapter contains the package outlines of the products.
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
FIGURE 7
Package Outline Raw Card G LG-DIM-240-7
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
6
Product Type Nomenclature
Qimondas nomenclature uses simple coding combined with some propriatory coding. Table 30 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 31 and for components in Table 32.
TABLE 30
Nomenclature Fields and Examples
Example for Field Number 1 Micro-DIMM DDR2 DRAM HYS HYB 2 64 18 3 T T 4 64/128 5 0 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
512/1G 16
TABLE 31
DDR2 DIMM Nomenclature
Field 1 2 3 4 Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Field 10
Description Speed Grade
Values -2.5F -2.5 -3 -3S -3.7 -5
Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
11
Die Revision
-A -B
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
TABLE 32
DDR2 DRAM Nomenclature
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 10 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B Unbuffered DDR2 SDRAM Module
Table of Contents
1 1.1 1.2 2 2.1 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 17 19 28 30
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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Internet Data Sheet
Edition 2006-10 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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